Design of Sub-mW RF CMOS Low-Noise Amplifiers

The quest for low power, low cost, and highly integrated transceivers has gained substantial momentum due to the explosion of wireless applications such as personal area networks and wireless sensor networks. This dissertation presents a comprehensive study and a design methodology for power-efficient CMOS radio-frequency (RF) low-noise amplifiers (LNAs). To demonstrate the design methodology, a sub-mW fully integrated narrow-band source degenerated cascode RF LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4GHz band. The LNA achieves a voltage gain of 22.7dB, noise figure (NF) of 2.8dB, 3 rd-order intercept point (IIP3) of +5.14dBm, and 1dB compression point (P1dB) of −10dBm, while consuming 943μW from a 1V supply. The main contributions of this work include: i) the introduction of a design methodology for power-efficient sub-mW source degenerated LNAs; ii) the collection of design graphs to facilitate the exploration of tradeoffs between LNA performance and power consumption; and iii) the use of an alternative analysis to find the dependency of gain, noise, and linearity on biasing conditions.